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Chapter 4:
IP Core Generation
This chapter provides information on how to generate the Block Viterbi Decoder IP core using the Diamond or isp-
LEVER software IPexpress tool, and how to include the core in a top-level design.
Licensing the IP Core
An IP core- and device-specific license is required to enable full, unrestricted use of the Block Viterbi Decoder IP
corein a complete, top-level design. Instructions on how to obtain licenses for Lattice IP cores are given at:
Users may download and generate the Block Viterbi Decoder IP core and fully evaluate the core through functional
simulation and implementation (synthesis, map, place and route) without an IP license. The Block Viterbi Decoder
IP corealso supports Lattice’s IP hardware evaluation capability, which makes it possible to create versions of the
IP core that operate in hardware for a limited time (approximately four hours) without requiring an IP license. See
“Hardware Evaluation” on page 27 for further details. However, a license is required to enable timing simulation, to
open the design in the Diamond or ispLEVER EPIC tool, and to generate bitstreams that do not include the hard-
ware evaluation timeout limitation.
Getting Started
The Block Viterbi Decoder IP core is available for download from Lattice’s IP server using the IPexpress tool. The
IP files are automatically installed using ispUPDATE technology in any customer-specified directory. After the IP
core has been installed, the IP core will be available in the IPexpress GUI dialog box shown in Figure 4-1 .
The IPexpress tool GUI dialog box for the Block Viterbi Decoder IP core is shown in Figure 4-1. To generate a spe-
cific IP core configuration the user specifies:
? Project Path – Path to the directory where the generated IP files will be loaded.
? File Name – “username” designation given to the generated IP core and corresponding folders and files.
? (Diamond) Module Output – Verilog or VHDL.
? (ispLEVER) Design Entry Type – Verilog HDL or VHDL.
? Device Family – Device family to which IP is to be targeted (e.g. LatticeSCM, Lattice ECP2M, LatticeECP3,
etc.). Only families that support the particular IP core are listed.
? Part Name – Specific targeted part within the selected device family.
IPUG32_02.7, June 2010
22
Block Viterbi Decoder User’s Guide
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相关PDF资料
VTERB-DECO-XP-N1
IP CORE VITERBI DECODER XPGA
VTP110F
POLYSWITCH PTC RESET 1.1A STRAP
VTP175LF
POLYSWITCH PTC RESET 1.75A STRAP
VTP210GF
POLYSWITCH PTC RESET 2.1A STRAP
VTP210SF
POLYSWITCH PTC RESET 2.1A STRAP
W51-A121B1-10
CIRCUIT BREAKER THERM 10A ILLUM
W54-XC2A4B10-40
CIRCUIT BREAKER THERMAL 40AMP
WV-089047-10-9
LABEL ID PRODUCTS
相关代理商/技术参数
VTERB-BLK-XM-U4
功能描述:编码器、解码器、复用器和解复用器 Block Viterbi Decoder RoHS:否 制造商:Micrel 产品:Multiplexers 逻辑系列:CMOS 位数: 线路数量（输入/输出）:2 / 12 传播延迟时间:350 ps, 400 ps 电源电压-最大:2.625 V, 3.6 V 电源电压-最小:2.375 V, 3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-44 封装:Tray
VTERB-DECO-O4-N1
功能描述:编码器、解码器、复用器和解复用器 Viterbi Decoder RoHS:否 制造商:Micrel 产品:Multiplexers 逻辑系列:CMOS 位数: 线路数量（输入/输出）:2 / 12 传播延迟时间:350 ps, 400 ps 电源电压-最大:2.625 V, 3.6 V 电源电压-最小:2.375 V, 3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-44 封装:Tray
VTERB-DECO-XP-N1
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VTESALLANF-155.520000
功能描述:155.52MHz LVPECL VCXO Oscillator Surface Mount 3.3V 100mA Enable/Disable 制造商:taitien 系列:VT 包装:剪带 零件状态:新产品 类型:VCXO 频率:155.52MHz 功能:启用/禁用 输出:LVPECL 电压 - 电源:3.3V 频率稳定度:±50ppm 工作温度:-40°C ~ 85°C 电流 - 电源（最大值）:100mA 等级:- 安装类型:表面贴装 大小/尺寸:0.276" 长 x 0.197" 宽（7.00mm x 5.00mm） 高度:0.075"（1.90mm） 封装/外壳:6-SMD，无引线（DFN，LCC） 电流 - 电源（禁用）（最大值）:- 标准包装:200
VTESFP4G
制造商:Promise Technologies 功能描述:SP.VTRAK.4GB SFP OPTICAL TRANSCEIVER.BOX - Bulk
VTEUALJANF-122.880000
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VTEUALJANF-153.600000
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VTEUALJANF-30.720000
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